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Espressif Systems /ESP32-C6 /EXTMEM /L1_CACHE_ACS_FAIL_INT_ENA

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Interpret as L1_CACHE_ACS_FAIL_INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_ICACHE0_FAIL_INT_ENA)L1_ICACHE0_FAIL_INT_ENA 0 (L1_ICACHE1_FAIL_INT_ENA)L1_ICACHE1_FAIL_INT_ENA 0 (L1_ICACHE2_FAIL_INT_ENA)L1_ICACHE2_FAIL_INT_ENA 0 (L1_ICACHE3_FAIL_INT_ENA)L1_ICACHE3_FAIL_INT_ENA 0 (L1_CACHE_FAIL_INT_ENA)L1_CACHE_FAIL_INT_ENA

Description

Cache Access Fail Interrupt enable register

Fields

L1_ICACHE0_FAIL_INT_ENA

The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0.
L1_ICACHE1_FAIL_INT_ENA

The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1.
L1_ICACHE2_FAIL_INT_ENA

Reserved
L1_ICACHE3_FAIL_INT_ENA

Reserved
L1_CACHE_FAIL_INT_ENA

The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache.

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Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data